for access to input/output bus

Full Title

Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 ; multiprocessor systems G06F15/16 ) > Handling requests for interconnection or transfer > for access to input/output bus

Child Classifications

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• G06F 13/22 using successive scanning, e.g. polling (G06F13/24 takes precedence)
• G06F 13/24 using interrupt (G06F13/32 takes precedence)
• G06F 13/28 using burst mode transfer, e.g. direct memory access , cycle steal (G06F13/32 takes precedence)
• G06F 13/32 using combination of interrupt and burst mode transfer