CPC Subgroup
H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Full Title
Automatic control of frequency or phase; Synchronisation > using a reference signal applied to a frequency- or phase-locked loop > Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop > using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) > a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
3 direct subcodes
Child Classifications
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- H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
Top Applicants
Top 10 applicants by patent filingsfor class H03, 2013–2023, worldwide · Source: EPO PATSTAT
- SAMSUNG ELECTRONICS COMPANY KR 7,293
- QUALCOMM US 7,085
- MURATA MANUFACTURING COMPANY JP 5,982
- HUAWEI TECHNOLOGIES COMPANY CN 4,641
- INTEL CORPORATION US 3,863
- TEXAS INSTRUMENTS US 3,409
- MURATA MANUFACTURING COMPANY 2,874
- SK HYNIX KR 2,644
- SKYWORKS SOLUTIONS US 2,545
- IBM (INTERNATIONAL BUSINESS MACHINES CORPORATION) US 2,437