G06F 12/10 Address translation
Introduced: January 1985
Full Title
Full titles differ between systems:
Accessing, addressing or allocating within memory systems or architectures > Addressing or allocation; Relocation > in hierarchically structured memory systems, e.g. virtual memory systems > Address translation
Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) > Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) > in hierarchically structured memory systems, e.g. virtual memory systems > Address translation
IPC and CPC are identically structured here. All 5 subcodes exist in both systems.
1 shared codes have differing titles between IPC and CPC.
IPC defines codes here since 2016.
Child Classifications
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- G06F 12/1009 using page tables, e.g. page table structures since 2016 IPC+CPC Available in IPC and CPC
- G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] since 2016 IPC+CPC Available in IPC and CPC
- G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems since 2016 IPC+CPC Available in IPC and CPC
- G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA] since 2016 IPC+CPC Available in IPC and CPC
- G06F 12/109 for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) since 2016 IPC+CPC Available in IPC and CPC