Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)

Full Title

Computer-aided design [CAD] > Circuit design > Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)

Child Classifications

Navigate with arrow keys, Enter to open

• G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• G06F 30/394 Routing (G06F30/396 takes precedence)
• G06F 30/396 Clock trees
• G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)