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PCE
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DIFF Subgroup
G09G 5/399

using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Introduced: January 2000

Full Title

Full titles differ between systems:

IPC:

Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators > characterised by the display of individual graphic patterns using a bit-mapped memory > Control of the bit-mapped memory > using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

CPC:

Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T) > characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory > Control of the bit-mapped memory > using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

No child classifications to compare. This is a leaf node in both IPC and CPC.