Control of the bit-mapped memory

Introduced: January 2000

Full Title

Full titles differ between systems:

IPC:

Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators > characterised by the display of individual graphic patterns using a bit-mapped memory > Control of the bit-mapped memory

CPC:

Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T) > characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory > Control of the bit-mapped memory

IPC and CPC are identically structured here. All 4 subcodes exist in both systems.

1 shared codes have differing titles between IPC and CPC.

IPC defines codes here since 2000.

Child Classifications

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G09G 5/391 Resolution modifying circuits, e.g. variable screen formats since 2000 IPC+CPC Available in IPC and CPC
G09G 5/393 Arrangements for updating the contents of the bit-mapped memory since 2000 IPC+CPC Available in IPC and CPC
G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) since 2000 IPC+CPC Available in IPC and CPC
G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers since 2000 IPC+CPC Available in IPC and CPC