DIFF Subgroup
G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
Introduced: January 2000
Full Title
Full titles differ between systems:
IPC:
Arrangements for writing information into, or reading information out from, a digital store > Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
CPC:
Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) > Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
No child classifications to compare. This is a leaf node in both IPC and CPC.