Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413)

Child Classifications

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• G11C 7/005 CPC only CPC only
• G11C 7/02 with means for avoiding parasitic signals IPC+CPC Available in IPC and CPC
• G11C 7/04 with means for avoiding disturbances due to temperature effects IPC+CPC Available in IPC and CPC
• G11C 7/06 Sense amplifiers; Associated circuits +3 CPC IPC+CPC Available in IPC and CPC
• G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers since 2000 +8 CPC IPC+CPC Available in IPC and CPC
• G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines since 2000 IPC+CPC Available in IPC and CPC
• G11C 7/14 Dummy cell management; Sense reference voltage generators since 2000 IPC+CPC Available in IPC and CPC
• G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters since 2000 IPC+CPC Available in IPC and CPC
• G11C 7/18 Bit line organisation; Bit line lay-out since 2000 IPC+CPC Available in IPC and CPC
• G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory since 2000 IPC+CPC Available in IPC and CPC
• G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management since 2000 +3 CPC IPC+CPC Available in IPC and CPC
• G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells since 2000 IPC+CPC Available in IPC and CPC