Multiple simultaneous or quasi-simultaneous cache accessing

Full Title

Accessing, addressing or allocating within memory systems or architectures > Addressing or allocation; Relocation > in hierarchically structured memory systems, e.g. virtual memory systems > Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches > Multiple simultaneous or quasi-simultaneous cache accessing

Classification Context

Section:

PHYSICS

Class:

COMPUTING OR CALCULATING; COUNTING

Subclass:

ELECTRIC DIGITAL DATA PROCESSING

Child Classifications

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• G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• G06F 12/0853 Cache with multiport tag or data arrays
• G06F 12/0855 Overlapped cache accessing, e.g. pipeline