using burst mode transfer, e.g. direct memory access, cycle steal

Introduced: January 1985

Last revised: January 2006

Full Title

Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units > Handling requests for interconnection or transfer > for access to input/output bus > using burst mode transfer, e.g. direct memory access, cycle steal

Classification Context

Section:: PHYSICS
Class:: COMPUTING OR CALCULATING; COUNTING
Subclass:: ELECTRIC DIGITAL DATA PROCESSING

1 direct subcode

Child Classifications

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G06F 13/3 with priority control