Circuit design at the digital level (reconfigurable circuits G06F30/34)

Full Title

Computer-aided design [CAD] > Circuit design > Circuit design at the digital level (reconfigurable circuits G06F30/34)

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• G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06F 30/33 Design verification, e.g. functional simulation or model checking
• G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• G06F 30/337 Design optimisation