G11C 2216/12 Reading and writing aspects of erasable programmable read-only memories
Full Title
Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups > Reading and writing aspects of erasable programmable read-only memories
Filing statistics
CPC G11C 2216/12 belongs to the parent subclass G11C, which recorded 152,594 patent applications worldwide between 2013 and 2023. Annual filings grew from 10,826 in 2013 to 13,151 in 2023 (+21%), peaking at 17,166 applications in 2021. The most active applicants in class G11 are MICRON TECHNOLOGY (12,397 applications), SAMSUNG ELECTRONICS COMPANY (12,238 applications) and SK HYNIX (11,371 applications).
Source: EPO PATSTAT, worldwide filings
9 direct subcodes
Child Classifications
Navigate with arrow keys, Enter to open
- G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
- G11C 2216/16 Flash programming of all the cells in an array, sector or block simultaneously
- G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously
- G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
- G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
- G11C 2216/24 Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously
- G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
- G11C 2216/28 Floating gate memory programmed by reverse programming, e.g. programmed with negative gate voltage and erased with positive gate voltage or programmed with high source or drain voltage and erased with high gate voltage
- G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
Top Applicants
Top 10 applicants by patent filingsfor class G11, 2013–2023, worldwide · Source: EPO PATSTAT
- MICRON TECHNOLOGY US 12,397
- SAMSUNG ELECTRONICS COMPANY KR 12,238
- SK HYNIX KR 11,371
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY TW 4,601
- INTEL CORPORATION US 3,874
- IBM (INTERNATIONAL BUSINESS MACHINES CORPORATION) US 3,866
- SANDISK TECHNOLOGIES US 3,151
- SK HYNIX 3,143
- SAMSUNG ELECTRONICS COMPANY 3,073
- WESTERN DIGITAL TECHNOLOGIES US 2,961