DIFF Subgroup
G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Introduced: January 2000
Full Title
Full titles differ between systems:
IPC:
Arrangements for selecting an address in a digital store > Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
CPC:
Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) > Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
No child classifications to compare. This is a leaf node in both IPC and CPC.