Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)

Child Classifications

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• G11C 8/005 CPC only CPC only
• G11C 8/02 using selecting matrix since 1974 IPC only IPC only
• G11C 8/04 using a sequential addressing device, e.g. shift register, counter since 1990 IPC+CPC Available in IPC and CPC
• G11C 8/06 Address interface arrangements, e.g. address buffers since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/10 Decoders since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/14 Word line organisation; Word line lay-out since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals since 2000 IPC+CPC Available in IPC and CPC
• G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access since 2000 IPC+CPC Available in IPC and CPC