DIFF Main Group
G11C 8/00 Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)
Introduced: July 1974
Title
Titles differ between systems:
IPC: Arrangements for selecting an address in a digital store
CPC: Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)
Full Title
Full titles differ between systems:
IPC:
Arrangements for selecting an address in a digital store
CPC:
Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)
Of 11 combined children, 9 exist in both systems.
1 codes are CPC-only extensions, 1 exist only in IPC.
IPC defines codes here since 1974.
Child Classifications
Navigate with arrow keys, Enter to open
- G11C 8/04 using a sequential addressing device, e.g. shift register, counter since 1990 IPC+CPC Available in IPC and CPC
- G11C 8/06 Address interface arrangements, e.g. address buffers since 2000 IPC+CPC Available in IPC and CPC
- G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines since 2000 IPC+CPC Available in IPC and CPC
- G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection since 2000 IPC+CPC Available in IPC and CPC
- G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups since 2000 IPC+CPC Available in IPC and CPC
- G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals since 2000 IPC+CPC Available in IPC and CPC
- G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access since 2000 IPC+CPC Available in IPC and CPC