DIFF Subgroup
H10B 41/43 comprising only one type of peripheral transistor
Introduced: January 2023
Full Title
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates > characterised by the peripheral circuit region > Simultaneous manufacture of periphery and memory cells > comprising only one type of peripheral transistor
IPC and CPC are identically structured here. All 4 subcodes exist in both systems.
IPC defines codes here since 2023.
Child Classifications
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- H10B 41/44 with a control gate layer also being used as part of the peripheral transistor since 2023 IPC+CPC Available in IPC and CPC
- H10B 41/46 with an inter-gate dielectric layer also being used as part of the peripheral transistor since 2023 IPC+CPC Available in IPC and CPC
- H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor since 2023 IPC+CPC Available in IPC and CPC
- H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor since 2023 IPC+CPC Available in IPC and CPC