Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Child Classifications

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• H10B 41/10 characterised by the top-view layout since 2023 IPC+CPC Available in IPC and CPC
• H10B 41/20 characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels since 2023 IPC+CPC Available in IPC and CPC
• H10B 41/30 characterised by the memory core region since 2023 IPC+CPC Available in IPC and CPC
• H10B 41/40 characterised by the peripheral circuit region since 2023 IPC+CPC Available in IPC and CPC
• H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region since 2023 IPC+CPC Available in IPC and CPC
• H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell since 2023 IPC+CPC Available in IPC and CPC
• H10B 41/70 the floating gate being an electrode shared by two or more components since 2023 IPC+CPC Available in IPC and CPC