DIFF Subgroup
H10B 41/40 characterised by the peripheral circuit region
Introduced: January 2023
Full Title
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates > characterised by the peripheral circuit region
IPC and CPC are identically structured here. All 2 subcodes exist in both systems.
IPC defines codes here since 2023.
Child Classifications
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- H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND since 2023 IPC+CPC Available in IPC and CPC
- H10B 41/42 Simultaneous manufacture of periphery and memory cells since 2023 IPC+CPC Available in IPC and CPC