Arrangements for selecting an address in a digital store

Classification Context

Section:

PHYSICS

Class:

INFORMATION STORAGE

Subclass:

STATIC STORES

Child Classifications

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• G11C 8/02 using selecting matrix
• G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• G11C 8/06 Address interface arrangements, e.g. address buffers
• G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 8/1 Decoders
• G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• G11C 8/14 Word line organisation; Word line lay-out
• G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• G11C 8/2 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access