Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Classification Context

Section:

ELECTRICITY

Class:

SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

Subclass:

ELECTRONIC MEMORY DEVICES

Child Classifications

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• H10B 41/1 characterised by the top-view layout
• H10B 41/2 characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
• H10B 41/3 characterised by the memory core region
• H10B 41/4 characterised by the peripheral circuit region
• H10B 41/5 characterised by the boundary region between the core region and the peripheral circuit region
• H10B 41/6 the control gate being a doped region, e.g. single-poly memory cell
• H10B 41/7 the floating gate being an electrode shared by two or more components