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CPC Subgroup Additional Only
H05K 2203/0733

Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls

Full Title

Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00 > Treatments involving liquids, e.g. plating, rinsing > Plating > Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls

Top Applicants

Top 10 applicants by patent filingsfor class H05, 2013–2023, worldwide · Source: EPO PATSTAT

  1. SAMSUNG ELECTRONICS COMPANY KR 9,981
  2. SAMSUNG DISPLAY KR 5,041
  3. LG ELECTRONICS KR 4,742
  4. PHILIP MORRIS PRODUCTS CH 4,411
  5. PANASONIC INTELLECTUAL PROPERTY JP 3,915
  6. PANASONIC INTELLECTUAL PROPERTY 3,471
  7. SAMSUNG ELECTRO-MECHANICS COMPANY KR 3,210
  8. MURATA MANUFACTURING COMPANY JP 3,191
  9. FUJI JP 2,987
  10. SIGNIFY HOLDING NL 2,907