IPC Subgroup
G09G 5/39 Control of the bit-mapped memory
Introduced: January 2000
Last revised: January 2006
Full Title
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators > characterised by the display of individual graphic patterns using a bit-mapped memory > Control of the bit-mapped memory
Classification Context
- Section:
- PHYSICS
- Class:
- EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- Subclass:
- ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
4 direct subcodes
Child Classifications
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- G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
- G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
- G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
- G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers