G11C 29/22 Accessing serial memories
Introduced: January 2006
Full Title
Full titles differ between systems:
Checking stores for correct operation; Testing stores during standby or offline operation > Detection or location of defective memory elements > Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing > Built-in arrangements for testing, e.g. built-in self testing [BIST] > Address generation devices; Devices for accessing memories, e.g. details of addressing circuits > Accessing serial memories
Checking stores for correct operation ; Testing stores during standby or offline operation > Detection or location of defective memory elements > Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing > Built-in arrangements for testing, e.g. built-in self testing [BIST] > Address generation devices; Devices for accessing memories, e.g. details of addressing circuits > Accessing serial memories
No child classifications to compare. This is a leaf node in both IPC and CPC.