Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Introduced: January 2006

Full Title

Full titles differ between systems:

IPC:

Checking stores for correct operation; Testing stores during standby or offline operation > Detection or location of defective memory elements > Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing > Built-in arrangements for testing, e.g. built-in self testing [BIST] > Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

CPC:

Checking stores for correct operation ; Testing stores during standby or offline operation > Detection or location of defective memory elements > Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing > Built-in arrangements for testing, e.g. built-in self testing [BIST] > Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Of 8 combined children, 5 exist in both systems.

3 codes are CPC-only extensions.

Note: 3 CPC extensions are marked as secondary classification only.

1 shared codes have differing titles between IPC and CPC.

Child Classifications

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G11C 2029/1802 2nd only CPC only CPC only
G11C 2029/1804 2nd only CPC only CPC only
G11C 2029/1806 2nd only CPC only CPC only
G11C 29/20 using counters or linear-feedback shift registers [LFSR] since 2006 IPC+CPC Available in IPC and CPC
G11C 29/22 Accessing serial memories since 2006 IPC+CPC Available in IPC and CPC
G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells since 2006 IPC+CPC Available in IPC and CPC
G11C 29/26 Accessing multiple arrays (G11C29/24 takes precedence) since 2006 +1 CPC IPC+CPC Available in IPC and CPC
G11C 29/30 Accessing single arrays since 2006 +1 CPC IPC+CPC Available in IPC and CPC