Layouts of interconnections

Full Title

Interconnections in chips, wafers or substrates > Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes > characterised by their conductive parts > Layouts of interconnections

Classification Context

Section:

ELECTRICITY

Class:

SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

Subclass:

GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS