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IPC Subclass
H10W

GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS

Introduced: January 2026

Classification Context

Section:
ELECTRICITY
Class:
SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
Subclass:
GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS

Description

H10W covers the physical packaging, interconnection architectures, connector designs, and structural elements applicable to semiconductor and solid-state devices classified under H10. This includes lead frames, bonding techniques, encapsulation materials, mounting substrates, and electrical connection schemes that are not device-type specific. The classification addresses generic constructional aspects that may apply across multiple semiconductor technologies (diodes, transistors, integrated circuits, etc.) when those aspects are not better covered by technology-specific classes.

Scope Notes

Glossary: via vias an electrically or thermally conductive connection that passes vertically through a layer. Examples include through-hole vias, blind vias, buried vias, and vias connecting between traces of the back-end-of-line [BEOL] metallisations.

Related Keywords

ASSEMBLING of semiconductor devices

17 direct subcodes

Child Classifications

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  • H10W 15/00 Highly-doped buried regions of integrated devices
  • H10W 29/00 Generic parts of integrated devices, not otherwise provided for
  • H10W 46/00 Marks applied to devices, e.g. for alignment or identification
  • H10W 78/00 Detachable holders for supporting packaged chips in operation
  • H10W 80/00 Direct bonding of chips, wafers or substrates
  • H10W 95/00 Packaging processes not covered by the other groups of this subclass
  • H10W 99/00 Subject matter not provided for in other groups of this subclass