DIFF Subgroup
H10W 20/43 Layouts of interconnections
Introduced: January 2026
Full Title
Interconnections in chips, wafers or substrates > Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes > characterised by their conductive parts > Layouts of interconnections
Of 1 combined children, 0 exist in both systems.
1 codes are CPC-only extensions.
Child Classifications
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