Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Full Title

Checking stores for correct operation; Testing stores during standby or offline operation > Detection or location of defective memory elements > Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing > Built-in arrangements for testing, e.g. built-in self testing [BIST] > Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Classification Context

Section:

PHYSICS

Class:

INFORMATION STORAGE

Subclass:

STATIC STORES

Child Classifications

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• G11C 29/2 using counters or linear-feedback shift registers [LFSR]
• G11C 29/22 Accessing serial memories
• G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• G11C 29/26 Accessing multiple arrays
• G11C 29/3 Accessing single arrays