Configurations of stacked chips

Full Title

Package configurations > Configurations of stacked chips

Classification Context

Section:

ELECTRICITY

Class:

SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

Subclass:

GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS

Child Classifications

Navigate with arrow keys, Enter to open

• H10W 90/22 the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
• H10W 90/24 at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
• H10W 90/26 the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
• H10W 90/28 the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape